this post was submitted on 13 Dec 2023
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End of my little TL;DR
So basically 'Even more + CFS'.
I want the opposite in a scheduler, I want bottleneck optimisation for AI and CAD.
I also wish there was an easy way to discover if my 12th gen i7 has AVX512 instructions fused off or just missing from microcode (early 12th gen had the instruction, but it was unofficial and discovered by motherboard makers. Intel later fused it off entirely according to some articles. Allegedly, all it took was running the microcode from the enterprise P-core which is identical on the consumer stuff.) I would love to have the option to set a CPUset affinity and isolation for llama.cpp (that automatically detects if the AVX ISA is available), and compare the inference speed with my present strategy.
My understanding is that the primary bottleneck in tensor table math is the L2 to L1 cache bus, but I'm basically just parroting that info on the edge of my mental understanding.
Thanks for the TLDR!